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A You have an option of setting trigger either EARLY that displays the values in the
ratio of (25% 75%), where the first % represents the % of data sampled before the
trigger point and the later % represent % sampled after the trigger point. The other
options available are CENTER(50% 50%) and LATE(75% 25%). You can select the
trigger position from Instrument -> Trigger Position and then selecting the required
Trigger position.
Q What is the recommended sampling rate?
A For an accurate reading, the sampling rate for a particular signal should be at least
twice the rate at which the signal is changing (According to the Nyquist theorem).
For example, a clock operating at 25 MHz should be sampled at least 50 MHz
frequency. Be aware that sampling at higher frequencies causes the Silicon
Explorer to consume more power.
Q What is the best way to find nets?
A The best way to find the nets in the Silicon Explorer is to use the Filter option
available in the software. You can search for the net you require by using the
*partial_name* in the filter, which would return all the signals having that
partial_name of the net. If you are using an HDL flow, it may be difficult to recognize
the net names you need to observe. Microsemi recommends that you use a
synthesis tool that can generate a gate-level schematic of your synthesized netlist
so that during probing, you can easily trace through the schematic and obtain the
net names from it.
Troubleshooting Hardware
Q How do I probe an SX-A device?
A The probing of an SX-A device requires special setup because it requires a 70 ohm
termination on all the probe connectors (TDI, TDO, TCK, TMS, PRA, PRB). The 70
ohm series termination is used to prevent data transmission corruption during
probing.
Q How do I tie the TRST pin during the probing using Silicon Explorer?
A TRST is an active low input. During JTAG mode and Silicon Explorer debugging
mode, JTAG state machine's reset must not be active, otherwise probe circuitry is
disabled. The recommendation for TRST pin in JTAG and Silicon Explorer is listed
below:
RTSX Rev0 - No TRST pin RTSX Rev1 - You must tie TRST pin high when doing
JTAG and Silicon Explorer.
RTSX Rev2 - You can leave the TRST pin floating (or drive it high - it must not be
driven low) when running JTAG or Silicon Explorer if “Reserve JTAG TRST” was
selected in Designer.
SXA - You can leave the TRST pin floating when running JTAG or Silicon Explorer
46
Silicon Explorer II User's Guide
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